In applications where a single voltage signal is to be compared with multiple thresholds, (i.e. an “n-bit” analog-to-digital converter), the input signal is applied to multiple operational amplifiers structured as comparator circuits. Each of the operational amplifiers has a separate threshold voltage applied to the input of the operational amplifiers.
Another application for using a signal voltage signal compared with two threshold values is in a buck DC-to-DC converter. The comparator compares the output voltage of the buck DC-to-DC converter with a reference voltage and determines if additional current needs to be applied to an inductor in the circuit as is known in the art. The switching frequency of the current to the inductor or from the inductor are generally fixed with the duty cycle of the switching frequency being adjusted or pulse width modulated to determine the amount of current flowing into the inductor and thus to the load circuit connected the output terminal of the DC-to-DC converter.
Generally, buck DC-to-DC converters operate in one of two different modes, a continuous mode and a discontinuous mode. When the buck DC-to-DC converter is operating at light load (a small load current), the current supplied from the supply voltage source is not supplied on each cycle and the current then supplied from the collapsing field of the inductor. Instead of being a pulse width modulated (PWM) conversion process in the continuous mode, the conversion in now based on a pulse frequency modulation (PFM) in the discontinuous mode. Often the discontinuous mode is used in portable electronics such as smart cellular telephone, tablet computers, digital readers, etc. as a “sleep mode”. The only current required by the system in these applications is monitoring current for system maintenance (i.e. system clocking and timers, cellular network monitoring, wireless network monitoring).
In the sleep mode, there are two different operating states. In the first state, the basic sleep state, a sleep comparator determines when the output voltage level of the buck DC-to-DC converter falls below a reference voltage level provided for the sleep comparator. When the output voltage level of the buck DC-to-DC converter has fallen below the reference voltage level, a PMOS transistor is activated to allow current to pass to an inductor of the buck DC-to-DC converter to increase the output voltage level appropriately.
In a second state of the sleep mode, a panic state, a panic comparator determines if the output voltage level of the buck DC-to-DC converter falls by a predetermine level below the reference voltage level (i.e. 10 mV). The panic comparator activates a panic signal and the panic comparator acts to change the drive scheme of the buck DC-to-DC converter to support a larger load current.
The sleep comparator is triggered regularly as part of the normal operation of the buck DC-to-DC converter. However, the buck DC-to-DC converter should only “panic” if the output voltage continues to fall. It is clearly important that these thresholds for the sleep comparator and the panic comparator are accurate, but it is more important that the gap between the thresholds is well controlled.
This situation occurs in many applications, where a lower threshold is used to trigger a corrective action, and a higher threshold is used as part of the normal operation. In these applications, the exact threshold of the comparators is less important than the difference between the two thresholds of the comparators.